This invention relates to volatile memory elements, and more particularly, to random access memory for integrated circuits such as configuration random access memory for programmable logic device integrated circuits.
Integrated circuits often contain volatile memory elements. In programmable logic devices, volatile memory elements are used to store configuration data. This type of memory is often referred to as configuration random-access memory (CRAM).
Programmable logic devices are a type of integrated circuit that can be customized in relatively small batches to implement a desired logic design. In a typical scenario, a programmable logic device manufacturer designs and manufactures uncustomized programmable logic device integrated circuits in advance. Later, a logic designer uses a logic design system to design a custom logic circuit. The logic design system uses information on the hardware capabilities of the manufacturer's programmable logic devices to help the designer implement the logic circuit using the resources available on a given programmable logic device.
The logic design system creates configuration data based on the logic designer's custom design. When the configuration data is loaded into the configuration random-access memory elements of one of the programmable logic devices, it programs the logic of that programmable logic device so that the programmable logic device implements the designer's logic circuit. The use of programmable logic devices can significantly reduce the amount of effort required to implement a desired integrated circuit design.
Conventional configuration random-access memory elements are formed using six-transistor cells. As semiconductor manufacturing technology improves, it is becoming possible to fabricate the transistors that make up the memory elements with increasingly small dimensions. It is generally desirable to shrink component sizes as much as possible to reduce costs and improve performance. It is may also be desirable to operate components at reduced power supply voltages to minimize power consumption.
As components shrink in size and as power supply voltages scale, a number of factors arise that can adversely impact memory element stability.
Memory element stability is affected by the amount of noise on each transistor. Noise may be produced by particle strikes such as strikes by neutrons or alpha particles. Noise may also be capacitively coupled into a memory element from nearby circuitry. When noise from these sources is introduced into a memory element, the memory element can erroneously change its state.
Memory element stability is also affected by transistor threshold voltage variations. Threshold voltage variations are a statistical byproduct of the discrete nature of the ions used when forming implant regions for a transistor.
To ensure that these factors do not make the memory elements unstable, conventional random-access memory elements have transistors with enlarged areas (i.e., enlarged gate widths). Transistors with enlarged areas store more critical charge than smaller transistors and are therefore less susceptible to noise such as noise from particle strikes. Transistors with enlarged areas are also less susceptible to threshold voltage variations and are better able to avoid interference from read and write operations performed on adjacent memory elements.
However, the need to increase the sizes of the transistors in conventional configuration random-access memory elements has an adverse impact on circuit real estate consumption. On a typical programmable logic device integrated circuit, the area consumed by the configuration random-access memory elements may be a significant fraction of the total area of the integrated circuit. As a result, the area penalty that is imposed by the need to enlarge transistor sizes to ensure adequate memory element stability may be nonnegligible.
It would therefore be desirable to be able to provide improved configuration random-access memory elements.